Intersil 6100
The Intersil 6100 family consists of a 12-bit microprocessor (the 6100) and a range of peripheral support and memory ICs developed by Intersil in the mid-1970s. The microprocessor implements the PDP-8 instruction set. As such it was sometimes referred to as the CMOS-PDP8. Since it was also produced by Harris Corporation, it was also known as the Harris HM-6100. The Intersil 6100 was introduced in the second quarter of 1975,[1][2] and the Harris version in 1976.[2]
The 6100 family was produced using CMOS rather than the bipolar and NMOS technologies used by most of its contemporaries (Z80, 8080, 6502, 6800, 9900, etc.). As a result of its CMOS technology and low clock speeds (8 MHz max. for the Harris HM-6100A), it had relatively low power consumption (less than 100 mW at 10 V/2 MHz) and could be operated from a single supply over the wide range of 4–11 V. Thus, it could be used in high reliability embedded systems without the need for any significant thermal management, if the rest of the system was also CMOS.
The 6100 was available to military specification and since it was dual sourced by Intersil and Harris, it was used in some military products as a low power alternative to the 8080, 6800 etc. Although it had a very simple instruction set and architecture, it was eminently suitable for use in embedded systems that had previously used discrete logic circuits and even Ledex motorised rotary switches or relay based logic controllers. In the 1980s there were still military systems in service that were using electro-mechanical relay logic controllers such as "Ledexes". When the equipment was being replaced in the 1980s, the 6100 was sometimes used; without the military equipment design constraints one of its more powerful contemporaries may have seemed more suitable.
The 6100 family was used in a number of commercial products, including the DECmate line, DEC's first attempt to produce a personal computer. Intersil sold the integrated circuits commercially through 1982 as the IM6100 family. It was not priced competitively, and the offering failed. The IBM PCs in 1981 cemented the doom of the "CMOS-8s".
Although this family of ICs had less logic than many competitors, and could have had smaller silicon and therefore undersold competitors, it used CMOS, then a larger technology, and failed.
Description
The 6100 is a 12-bit CPU that closely emulates the PDP-8 (See PDP-8 for a more complete discussion). It has three primary registers: PC (program counter), 12-bit AC (accumulator), and MQ. All two-operand instructions read the AC and MQ and write back to the AC. There is no stack pointer; subroutines return to their callers by jumping back into the main code, typically by storing the return address in the first word of the subroutine itself. (Not good for programs in ROM.)
Conditionals in the 6100 only allow the next instruction to be skipped. Branches are constructed with a conditional and a following jump. There is only one maskable interrupt. When the interrupt is tripped, the CPU stores the current PC in 0000, and then jumps to the location stored in 0001. The interrupt can be disabled or enabled using the IOF and ION (or SKON) instructions.
The 6100 has a 12-bit data/address bus, limiting RAM to only 4K words (6 KB). Memory references are 7-bit, offset either from address 0, or from the PC page base address (obtained by setting the seven least significant bits of PC to zero). Memory could be expanded using the optional 6102 support chip, which added three address lines and thus expanded memory to 32K words (48 KB) in the same way that the PDP-8/E expanded the PDP-8. The 6102 has two internal registers, IFR (instruction field register) and DFR (data field register), that offset the 4K page when the CPU accesses memory.
Versions and supporting hardware
Intersil offered a variety of related chips[3] to support 6100 systems. The IM6100 CPU implements a straight-8 (basic PDP-8 without memory mapping hardware). The IM6101 PIE (Programmable Interface Element) is a basic PDP-8 I/O port. The IM6102 MEDIC (Memory Extension, DMA Controller, Interval Timer) converts an IM6100 into something resembling a PDP-8/E's CPU. The IM6103 PIO (Parallel Input-Output Port), and the IM6402 or IM6403 UART are basic PDP-8 I/O devices on ICs.
Intersil also offered compatible sizes of RAM and ROM: the IM6551 and IM6561 (1 Kbit, 256×4) SRAM, the IM6512 (768 Bit, 64x12) SRAM, and the IM6312 (12 Kbit, 1024×12) mask programmable PROM.
A selection of these components were offered as the Intersil 6801 CMOS Family Sampler Kit with the 6960 – Sampler PC Board, a single-board system including the IM6100 CPU, IM6101 PIE, the IM6312 ODT (Octal Debugging Technique) Monitor ROM, three 256×4 CMOS RAMs and a UART IM6403.
The basic 6100 was later upgraded to the 6120, with the 6102 memory controller built-in.
References
- ↑ "Microprocessors — The Explosion 1975-1976". AntiqueTech.com. 2009-04-21. Retrieved 2010-12-27.
- 1 2 Bell, Gordon (1980), Family Tree of Digital's Computers, (Poster), Digital Equipment Corporation, retrieved 2010-12-27
- ↑ Intersil, Data Book 1981, pages 8-77 to 8-211.
External links
- "Intersil 6100 microprocessor architecture", CPU World
- Intersil, "IM6100 CMOS Family Sampler"