OpenVera
OpenVera is a hardware verification language developed and managed by Synopsys. OpenVera is an interoperable, open hardware verification language for testbench creation. The OpenVera language was used as the basis for the advanced verification features in the IEEE Std. 1800 SystemVerilog standard, for the benefit of the entire verification community including companies in the semiconductor, systems, IP and EDA industries along with verification services.
The OpenVera language reference manual (LRM) can be obtained at no cost, but modifications to the language must go through Synopsys.
Vendors supporting OpenVera
- Nusym Technology
- Synopsys
- Axiom Design Automation
- Reference Verification Methodology (RVM)
See also
External links
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