Place and route

Place and route is a stage in the design of printed circuit boards, integrated circuits, and field-programmable gate arrays. As implied by the name, it is composed of two steps, placement and routing. The first step, placement, involves deciding where to place all electronic components, circuitry, and logic elements in a generally limited amount of space. This is followed by routing, which decides the exact design of all the wires needed to connect the placed components. This step must implement all the desired connections while following the rules and limitations of the manufacturing process.

Place and route is used in several contexts:

• Printed circuit boards, during which components are graphically placed on the board and the wires drawn between them
• Integrated circuits, during which a layout of a larger block of the circuit or the whole circuit is created from layouts of smaller sub-blocks
• FPGAs, during which logic elements are placed and interconnected on the grid of the FPGA

These processes are similar at a high level, but the actual details are very different. With the large sizes of modern designs, this operation is usually performed by electronic design automation (EDA) tools.

In all these contexts, the final result when placing and routing is finished is the layout, a geometric description of the location and rotation of each part, and the exact path of each wire connecting them.

Occasionally some people call the entire place-and-route process layout.

Printed circuit board

The design of a printed circuit board comes after the creation of a schematic and generation of a netlist. The generated netlist is then read into a layout tool and associated with part footprints from a library. Placing and routing can now start.

Placing and routing is generally done in two steps. Placing the components comes first, then routing the connections between the components. The component placement is not absolute during the routing phase, as it may still be changed by moving and rotating, especially with designs using more complex components such as FPGAs or microprocessors. Their large number of signals, and their signal integrity needs may require optimization of the placement.^[1]

The resulting design is then output in RS-274X Gerber format to load in the CAM system of the manufacturer.

Field-programmable gate array

The process of placing and routing for an FPGA is generally not performed by a person, but uses a tool provided by the FPGA Vendor or another software manufacturer. The need for software tools is because of the complexity of the circuitry within the FPGA, and the function the designer wishes to perform. FPGA designs are described using logic diagrams containing digital logic, Very High Speed Integrated Circuits Hardware Description Language (VHDL), and Verilog. These will then be put through an automated place-and-route procedure to generate a pinout, which will be used to interface with the parts outside of the FPGA.^[1]

Integrated circuits

The IC place-and-route stage typically starts with one or more schematics, HDL files, or pre-routed IP cores, or some combination of all three. It produces an IC layout that is automatically converted to a mask work in the standard GDS II or the OASIS Format.^[2]

History

The final layout of early ICs and PCBs was stored as a tape-out of Rubylith on transparent film.

Gradually, electronic design automation automated more and more of the place-and-route work. At first, it merely sped up the process of making many small edits without spending a lot of time peeling up and sticking down the tape. Later design rule checking sped up the process of checking for the most common sorts of errors. Later auto routers speed up the process of routing.

Some people hope that further improvements in autoplacers and autorouters will eventually produce good layouts without any human manual intervention. Further automation leads to the idea of a silicon compiler.

References

1. "FPGA/PCB Co-Design Increases Fabrication Yields". Printed Circuit Design and Fabrication. Retrieved 2008-07-24.
2. A. Kahng, J. Lienig, I. Markov, J. Hu: "VLSI Physical Design: From Graph Partitioning to Timing Closure", Springer (2011), ISBN 978-90-481-9590-9, pp. 7-11.