C-element

Delays in the naïve (Earle latch based) implementation and environment
Timing diagram of a C-element and inclusive OR gate
Majority gate realization of C-element and inclusive OR gate (a); Realizations proposed by Maevsky (b), Starodoubtsev (c) and Murphy (d)
Static implementations of two- and three input C-element [1][2][3]
Semi-static implementations of two- and multiple input C-element [3] based on the ideas from [4][5][6]
David cell (a) and its fast implementations: gate-level (b) and transistor-level (c) [7]

The Muller C-element (C-gate, Hysteresis flip-flop or sometimes, coincident flip-flop, two-hand safety circuit) is a small digital block widely used in design of asynchronous circuits and systems. It has been specified formally in 1955 by David E. Muller [8] and first used in ILLIAC II computer.[9] In terms of the theory of lattices, the C-element is a semimodular distributive circuit, whose operation in time is described by Hasse diagram.[10][11][12] The C-element is closely related to the Rendezvous [13] and Join [14] elements, where an input is not allowed to change twice in succession. For asynchronous circuits, where relations betweens some delays are known in advance, the requirements for C-element can be less stiff.[15] Earlier techniques for implementing the C-element [16][17] include Schmidt trigger,[18] Eccles-Jordan flip-flop and last moving point flip-flop.

Truth table and delay assumptions

For two input signals the C-element is defined by the equation , which corresponds to the following truth table:

0 0 0
0 1
1 0
1 1 1

This table can be turned into a circuit using the Karnaugh map. However, the obtained implementation is naïve, since nothing is said about delay assumptions. To understand under what conditions the obtained circuit is workable, it is necessary to do additional analysis, which reveals that

Thus, the naïve implementation is correct only for slow environment.[19]

Note that the definition of C-element can be easily generalized for multiple-valued logic or even for continuous signals . For example, the truth table for a balanced ternary C-element with two inputs is

-1 -1 -1
-1 0
-1 1
0 -1
0 0 0
0 1
1 -1
1 0
1 1 1

Implementations of the C-element

Depending on the requirements to the switching speed and power consumption, the C-element can be realized as a coarse- or fine-grain circuit.

Gate-level implementations

A C-element can be built using only NAND, NOR and inverter gates. Many different implementations have been proposed.[20][21][22][23][24] The so-called Maevsky's implementation [25][26][27] is a speed-independent (internally non-distributive) circuit loosely based on Varshavsky et al.,[28] which in turn, is an improved version of.[29] The 3NAND gate in this circuit can be safely replaced by two 2NAND gates. Note that sometimes it is advisable to introduce non-distributivity to increase concurrency. The C-element synthesized by Starodoubtsev et al. using Taxogram language is presented in.[30] This circuit coincides with that attributed (without reference) to Bartky in [25] and can operate without the input latch. The approach proposed in [30] is valuable by that the synthesis is done using 2NAND and 2NOR gates only. Yet another version of the C-element built on two RS latches has been synthesized by Murphy [31] using Petrify tool.

Static and semi-static implementations

In his report [8] Muller proposed to realize C-element as a majority gate with feedback. However, to alleviate hazards, which are linked with skews of internal delays, the majority gate must have as small number of transistors as possible.[32][33] Generally, C-elements with different timing assumptions [34] can be built on AND-OR-Invert (AOI) [35][36] or its dual, OR-AND-Invert (OAI) gate [37][38] and inverter.

Note that connecting an additional majority gate to the inverted output of C-element, we obtain inclusive OR (EDLINCOR) function:[39][40] . Note also that some simple asynchronous circuits like pulse distributors [41] can be built solely on majority gates.

Since the majority gate is a particular case of threshold gate, any of known realizations of threshold gate [42] can in principle be used for building a C-element. In the multiple-valued case however, connecting the output of majority gate to one or several inputs may have no desirable effect. For example, using the ternary majority function defined as:[43]

does not lead to the ternary C-element specified by the truth table, if the sum is not split into pairs. However, even without such a splitting two ternary majority functions are suitable for building a ternary inclusive OR gate.

Semi-static C-element stores its previous state using two cross-coupled inverters, similar to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-down networks. If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either or ground, and so the weak inverter dominates and the latch outputs its previous state.

Note that both the Maevsky and Starodoubtsev circuits are based actually on so-called David cell.[44] Its fast transistor-level implementation is used in the semi-static C-element proposed in.[45] Yet another semi-static circuit using pass transistors has been proposed in.[46]

There are also versions of semi-static C-element built on devices with negative differential resistance (NDR).[47][48] It should be noted however, that NDR is usually defined for small signal. So, it is difficult to expect that such a C-element will operate in full range of voltages or currents.

Other modern technologies suitable for realizing asynchronous primitives including C-element, are carbon nanotubes,[49] single electron tunneling devices,[50] quantum dots [51] and molecular nanotechnology.[52]

Advanced topics

Some speed-independent approaches [53][54] assume that zero-delay input inverters are available on all gates, which is a violation of true speed-independence but is fairly safe in practice. Other examples of using this assumption can be found.[55][56][57]

References

  1. ↑ I. E. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, no. 6, pp. 720-738, 1989.
  2. ↑ C. H. van Berkel, "Beware the isochronic fork," Report UR 003/91, Philips Research Laboratories, 1991.
  3. 1 2 V. B. Marakhovsky, Logic design of asynchronous circuits. Slides on the course. CS&SE Department, SPbPU.
  4. ↑ V. I. Varshavsky, "β-driven threshold elements," IEEE Great Lakes Symposium on VLSI 1998, pp. 52-58.
  5. ↑ V. I. Varshavsky, N. M. Kravchenko, V. B. Marakhovsky, B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1562964, Jul. 5, 1990.
  6. ↑ K. J. Schultz, R. J. Francis, K. C. Smith, "Ganged CMOS: trading standby power for speed," IEEE Journal of Solid-State Circuits, vol. 25, no. 3, pp. 870-873, 1990.
  7. ↑ A. Bystrov, A. Yakovlev, Asynchronous circuit synthesis by direct mapping: Interfacing to environment. Technical Report, CS Department, University of Newcastle upon Tyne, October 2001.
  8. 1 2 D. E. Muller, Theory of asynchronous circuits. Report no. 66, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1955.
  9. ↑ H. C. Breadley, "ILLIAC II — A short description and annotated bibliography," IEEE Transactions on Electronic Computers, vol. EC-14, no. 3, pp. 399-403, 1965.
  10. ↑ D. E. Muller and W. S. Bartky, "A theory of asynchronous circuits," Int. Symposium on the Switching Theory in Harvard University, pp. 204-243, 1959.
  11. ↑ W. J. Poppelbaum, Introduction to the Theory of Digital Machines. Math., E.E. 294 Lecture Notes, University of Illinois at Urbana-Champaign.
  12. ↑ J. Gunawardena, "A generalized event structure for the Muller unfolding of a safe net," Int. Conference on Concurrency Theory (CONCUR) 1993, pp. 278-292.
  13. ↑ M. J. Stucki, S. M. Ornstein, W. A. Clark, "Logical design of macromodules," in Proceedings of AFIPS 1967, pp. 357-364.
  14. ↑ J. C. Ebergen, J. Segers, I. Benko, "Parallel Program and Asynchronous Circuit Design," Workshops in Computing, pp. 50-103, 1995.
  15. ↑ H. Park, A. He, M. Roncken and X. Song, "Semi-modular delay model revisited in context of relative timing," IET Electronics Letters, vol. 51, no. 4, pp. 332-334, 2015.
  16. ↑ Technical Progress Report, Jan. 1959, University of Illinois at Urbana-Champaign.
  17. ↑ W . J. Poppellbaum, N. E. Wiseman, "Circuit design for the new Illinois computer," Report no. 90, University of Illinois at Urbana-Champaign, 1959.
  18. ↑ N. P. Singh, A design methodology for self-timed systems. MSc thesis, MIT, 1981, 98 p.
  19. ↑ J. Cortadella, M. Kishinevsky, Tutorial: Synthesis of control circuits from STG specifications. Summer school, Lyngby, 1997
  20. ↑ B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1096759, Jun. 7, 1984
  21. ↑ B. S. Tsirlin, "Multiple input H flip-flop," USSR author's certificate SU1162019, Jun. 15, 1985
  22. ↑ G. S. Brailovsky, L. Ya. Rozenblyum, B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1277385, Jan. 15, 1986
  23. ↑ B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1324108, Jul. 15, 1987
  24. ↑ G. S. Brailovsky, L. Ya. Rozenblyum, B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1432733, Oct, 23, 1988
  25. 1 2 M. Kuwako, T. Nanya, "Timing-reliability evaluation of asynchronous circuits based on different delay models," IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC) 1994, pp.22-31.
  26. ↑ J. A. Brzozowski, K. Raahemifar, "Testing C-elements is not elementary," Working Conference on Asynchronous Design Methodologies (ASYNC) 1995, pp. 150-159.
  27. ↑ S. Golubcovs, A. Alekseyev, A. Mokhov, A. Yakovlev, "Asynchronous circuit development with Workcraft," Technical Report NCL-EECE-MSD-TR-2011-174, University of Newcastle upon Tyne, 2011
  28. ↑ V. I. Varshavsky, O. V. Maevsky, Yu. V. Mamrukov, B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1081801, Mar. 23, 1984
  29. ↑ G. Brailovsky, "H flip-flop," USSR author's certificate SU945960, Jul. 23, 1982
  30. 1 2 N. A. Starodoubtsev, S. A. Bystrov, "Monotonic behavior refinement for synthesis of two-input-gate asynchronous circuits," IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2004, vol. I, pp. I-521-524.
  31. ↑ J. P. Murphy, "Design of latch-based C-element," Electronics Letters, vol. 48, no. 19, 2012, pp. 1190-1191
  32. ↑ D. Hampel, K. Prost, and N. Scheingberg, "Threshold logic using complementary MOS device," Patent US3900742, Aug. 19, 1975.
  33. ↑ D. Doman, Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon. Wiley, 2012, 327p.
  34. ↑ K. S. Stevens, R. Ginosar and S. Rotem, "Relative timing [asynchronous design]," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, pp. 129-140, 2003.
  35. ↑ H. Zemanek, "Sequentielle asynchrone Logik," Elektronische Rechenanlagen, vol. 4, no. 6, pp. 248–253, 1962. also available in Russian as Г. Цеманек, "Последовательная асинхронная логика," Mеждународный симпозиум ИФАК Теория конечных и вероятностных автоматов 1962, стр. 232—245.
  36. ↑ W. Fleischhammer, "Improvements in or relating to asynchronous bistable trigger circuits," UK patent specification GB1199698, Jul. 22, 1970
  37. ↑ T.-Y. Wuu and S. B. K. Vrudhula, "A design of a fast and area efficient multi-input Muller C-element," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 2, pp. 215-219, 1993.
  38. ↑ H. K. O. Berge, A. Hasanbegovic, S. Aunet, "Muller C-elements based on minority-3 functions for ultra low voltage supplies," IEEE Int. Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) 2011, pp. 195-200.
  39. ↑ D. A. Pucknell, "Event-driven logic (EDL) approach to digital systems representation and related design processes," IEE Proceedings E, Computers and Digital Techniques, vol. 140, no. 2, pp. 119—126, 1993.
  40. ↑ A. Yakovlev, M. Kishinevsky, A. Kondratyev, L. Lavagno, M. Pietkiewicz-Koutny, "On the models for asynchronous circuit behaviour with OR causality, " Formal Methods in System Design, vol. 9, no. 3, pp. 189—233. 1996.
  41. ↑ J. C. Nelson, Speed-independent counting circuits. Report no. 71, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1956.
  42. ↑ V. Beiu, J. M. Quintana, M. J. Avedillo, "VLSI implementations of threshold logic - A comprehensive survey," IEEE Transactions on Neural Networks, vol. 14, no. 5, pp. 1217-1243, 2003.
  43. ↑ V. Varshavsky, B. Ovsievich, "Networks composed of ternary majority elements," IEEE Transactions on Electronic Computers, vol. EC-14, no. 5, pp.730-733, 1965.
  44. ↑ R. David. Réalisation de systèmes séquentiels asynchrones par interconnexion simple de cellules séquentielles identiques. Modélisation et simulation. D.Sc. thèse in Physique, Université Joseph-Fourier, Grenoble, 1969, 170 p.
  45. ↑ S. M. Fairbanks, "Two-stage Muller C-element," United States Patent US6281707, Aug. 28, 2001
  46. ↑ A. Morgenshtein, M. Moreinis, R. Ginosar, "Asynchronous gate-diffusion-input (GDI) circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.12, no.8, pp. 847-856, 2004
  47. ↑ C.-H. Lin, K. Yang, A. F. Gonzalez, J. R. East, P. Mazumder, G. I. Haddad, "InP-based high speed digital logic gates using an RTD/HBT heterostructure," Int. Conference on Indium Phosphide and Related Materials (IPRM) 1999, pp. 419-422.
  48. ↑ P. Glosekotter, C. Pacha, K. F. Goser, W. Prost, S. Kim, H. van Husen, et al., "Asynchronous circuit design based on the RTBT monostable-bistable logic transition element (MOBILE)," Symposium Integrated Circuits and Systems Design 2002, pp. 365-370.
  49. ↑ B. Liu, "Nanoelectronic Design Based on a CNT Nano-Architecture," Chap. 19 in VLSI book, ed. Z. Wang, pp. 375-408, InTech, 2010.
  50. ↑ S. Safiruddin, S. D. Cotofana, "Building blocks for delay-insensitive circuits using single electron tunneling devices," IEEE Conference on Nanotechnology 2007, pp. 704-708.
  51. ↑ V. I. Varshavsky, "Logic design and quantum challenge," Int. Workshop on Physics and Computer Modeling of Devices Based on Low-Dimensional Structures 1995, pp. 134-146.
  52. ↑ A. J. Martin, P. Prakash, "Asynchronous nano-electronics: Preliminary investigation," IEEE Int. Symposium on Asynchronous Circuits and Systems (ASYNC) 2008, pp. 58-68.
  53. ↑ P. Beerel and T. H.-Y. Meng. Automatic gate-level synthesis of speed-independent circuits," IEEE/ACM Int. Conference on Computer-Aided Design (ICCAD) 1992, pp. 581–587.
  54. ↑ A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, "Basic gate implementation of speed-independent circuits," ACM Design Automation Conference (DAC) 1994, pp. 56-62.
  55. ↑ A. V. Yakovlev, A. M. Koelmans, A. Semenov, D. J. Kinniment, "Modelling, analysis and synthesis of asynchronous control circuits using Petri nets," Integration, the VLSI Journal, vol. 21, no. 3, pp. 143—170, 1996.
  56. ↑ D. Sokolov, J. Murphy, A. Bystrov, A. Yakovlev, "Improving the security of dual-rail circuits," Technical report NCL-EECE-MSD-TR-2004-101, University of Newcastle upon Tyne, 2004.
  57. ↑ A. Mokhov, V. Khomenko, D. Sokolov and A. Yakovlev, "On dual-rail control logic for enhanced circuit robustness," IEEE Int. Conference on Application of Concurrency to System Design (ACSD) 2012, pp. 112-121.

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