Physical Coding Sublayer

The Physical Coding Sublayer (PCS) is a networking protocol sublayer in the Fast Ethernet, Gigabit Ethernet, and 10 Gigabit Ethernet standards. It resides at the top of the physical layer (PHY), and provides an interface between the Physical Medium Attachment (PMA) sublayer and the Media Independent Interface (MII). It is responsible for data encoding/decoding, scrambling/descrambling, alignment marker insertion/removal, block and symbol redistribution, and lane block synchronization and deskew.[1]

Description

The Ethernet PCS sublayer is at the top of the Ethernet physical layer (PHY). The hierarchy is as follows:

Specifications

Fast Ethernet

Gigabit Ethernet

10 Gigabit Ethernet

25 Gigabit Ethernet

40/100 Gigabit Ethernet

Lattice Semiconductor multi-protocol

"PCS logic can be configured to support numerous industry-standard, high-speed serial data transfer protocols."[9]

References

  1. Spurgeon, Charles (2014). Ethernet: The Definitive Guide. O'Reilly. p. 198.
  2. IEEE 802.3 Clause 24.1.4.1
  3. IEEE 802.3-2012 Clause 36
  4. IEEE 802.3-2012 Clause 40
  5. IEEE 802.3 48. Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) sublayer, type 10GBASE-X
  6. IEEE 802.3 Clause 55.3.2
  7. "IEEE 802.3by 25G Ethernet TF, A BASELINE PROPOSAL FOR RS, PCS, AND FEC" (PDF). 2015-01-12. Retrieved 2016-08-06.
  8. IEEE 802.3 Clauses 82-89
  9. "LatticeECP3 SERDES/PCS Usage Guide" (PDF). Lattice semiconductor Corporation: p 8–1. Archived from the original (PDF) on 2014-07-17. Retrieved 2014-09-03.

External links

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