Blackfin

This article is about the DSP microprocessor. For other uses, see Blackfin (disambiguation).
Blackfin
Designer Analog Devices
Bits 32-bit
Introduced 2000 (2000)
Design RISC
Type Register-Register
Encoding Variable (16- or 32-bit general purpose, or 64-bit parallel issue of 1 × 32-bit instruction + 2 × 16-bit instructions)
Branching Condition code
Endianness Little
Registers
General purpose 8 × 32-bit data registers, 2 × 40-bit accumulators, 6 address registers, stack pointer, frame pointer
Blackfin

ADI Blackfin Logo
Produced From 2008 to Present
Marketed by Analog Devices
Designed by Analog Devices
Common manufacturer(s)

The Blackfin is a family of 16- or 32-bit microprocessors developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point digital signal processor (DSP) functionality supplied by 16-bit Multiply–accumulates (MACs), accompanied on-chip by a small microcontroller.[1] It was designed for a unified low-power processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding.[2][3] There are several hardware development kits for the Blackfin. Open-source operating systems for the Blackfin include uClinux.

Architecture details

Blackfin processors use a 32-bit RISC microcontroller programming model on a SIMD architecture, which was co-developed by Intel and Analog Devices, as MSA (Micro Signal Architecture).

The architecture was announced in December 2000, and first demonstrated at the Embedded Systems Conference in June, 2001.

It incorporates aspects of ADI's older SHARC architecture and Intel's XScale architecture into a single core, combining digital signal processing (DSP) and microcontroller functionality. There are many differences in the core architecture between Blackfin/MSA and XScale/ARM or SHARC, but the combination was designed to improve performance, programmability and power consumption over traditional DSP or RISC architecture designs.

The Blackfin architecture encompasses various CPU models, each targeting particular applications.[4]

Architecture features

Core features

mounted Blackfin BF535

What is regarded as the Blackfin "core" is contextually dependent. For some applications, the DSP features are central. Blackfin has two 16-bit hardware MACs, two 40-bit ALUs, and a 40-bit barrel shifter. This allows the processor to execute up to three instructions per clock cycle, depending on the level of optimization performed by the compiler or programmer. Two nested zero-overhead loops and four circular buffer DAGs (data address generators) are designed to assist in writing efficient code requiring fewer instructions. Other applications utilize the RISC features, which include memory protection, different operating modes (user, kernel), single-cycle opcodes, data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals.

The ISA is designed for a high level of expressiveness, allowing the assembly programmer (or compiler) to optimize an algorithm for the hardware features present.

Memory and DMA

The Blackfin uses a byte-addressable, flat memory map. Internal L1 memory, internal L2 memory, external memory and all memory-mapped control registers reside in this 32-bit address space, so that from a programming point of view, the Blackfin has a Von Neumann architecture.

The L1 internal SRAM memory, which runs at the core-clock speed of the device, is based on a Harvard architecture. Instruction memory and data memory are independent and connect to the core via dedicated memory buses, designed for higher sustained data rates between the core and L1 memory.

Portions of instruction and data L1 SRAM can be optionally configured as cache independently.

Certain Blackfin processors also have between 64KB and 256KB of L2 memory. This memory runs slower than the core clock speed. Code and data can be mixed in L2.

Blackfin processors support a variety of external memories including SDRAM, DDR-SDRAM, NOR flash, NAND flash and SRAM. Some Blackfin processors also include mass-storage interfaces such as ATAPI and SD/SDIO. They can support hundreds of megabytes of memory in the external memory space.

Coupled with the core and memory system is a DMA engine that can operate between any of its peripherals and main (or external) memory. The processors typically have a dedicated DMA channel for each peripheral, which designed for higher throughput for applications that can utilise it, such as real-time standard-definition (D1) video encoding and decoding.

Microcontroller features

The architecture of Blackfin contains the usual CPU, memory, and I/O that is found on microprocessors or microcontrollers. These features enable operating systems.

Media-processing features

The Blackfin instruction set contains media-processing extensions to help accelerate pixel-processing operations commonly used in video compression and image compression and decompression algorithms.

Peripherals

Blackfin processors contain an array of connectivity peripherals, depending on the specific processor:

All of the peripheral control registers are memory-mapped in the normal address space.

Development tools

Blackfin BF537 EZ-Kit-Lite evaluation platform

ADI provides its own software development toolchains. The original VisualDSP++ IDE is still supported (its last release was 5.1.2 in October 2014), but is approaching end of life and has not had support added for the new BF6xx and BF7xx processors. The newer toolchain is CrossCore Embedded Studio, which uses upgraded versions of the same compiler and tools internally, but with a UI based on Eclipse CDT. No free version of either tool is available; a single-user license for VisualDSP++ costs $3500 USD, and CrossCore Embedded Studio $995 USD.

Other options include Green Hills Software's MULTI IDE, the GNU GCC Toolchain for the Blackfin processor family, the OpenEmbedded project, National Instruments' LabVIEW Embedded Module, or Microsoft Visual Studio through use of AxiomFount's AxiDotNet software.

Supported operating systems, RTOSs and kernels

Blackfin supports several commercial and open-source operating systems.

OS/RTOS/Kernels on Blackfin
Title License Comments
Linux kernel GNU General Public License Integrated into mainline kernel, distributed as part of the μClinux
ThreadX[5] Proprietary
Nucleus Proprietary
Fusion RTOS Proprietary
µC/OS-II[6] Proprietary
INTEGRITY[7] Proprietary
RTEMS GNU General Public License
RTXC Quadros Proprietary
T2 SDE GNU General Public License
VDK Proprietary ADI's real-time kernel. Ships with VisualDSP++.
TOPPERS/JSP GNU General Public License
scmRTOS MIT License Single-Chip Microcontroller Real-Time Operating System"
.NET Micro FrameworkApache License 2.0 Stand-alone version from Microsoft. Integrated version from AxiomFount.
SCIOPTA Proprietary Certified according to IEC61508 for functional safety.

See also

References

  1. "Archived copy". Archived from the original on April 17, 2011. Retrieved April 9, 2011.
  2. "H.264 BP/MP Encoder". Analog Devices. Retrieved 2014-09-03.
  3. "H.264 BP/MP Decoder Library". Analog Devices. Retrieved 2014-09-03.
  4. "Blackfin Processors | Analog Devices". Analog.com. Retrieved 2016-06-24.
  5. "Real-Time Operating Systems for Embedded Development, Real Time System By Express Logic". Rtos.com. Retrieved 2016-06-24.
  6. "Real-Time Kernels". Micrium.com. Retrieved 2016-06-24.
  7. "INTEGRITY Real-time Operating System". Ghs.com. Retrieved 2016-06-24.

External links

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