SPARC

For other uses, see SPARC (disambiguation).
SPARC
Designer Sun Microsystems (acquired by Oracle Corporation)
Bits 64-bit (32 → 64)
Introduced 1987 (shipments)
Version V9 (1993) / OSA2015
Design RISC
Type Register-Register
Encoding Fixed
Branching Condition code
Endianness Bi (Big → Bi)
Page size 8 KB (4 KB → 8 KB)
Extensions VIS 1.0, 2.0, 3.0, 4.0
Open Yes, and royalty free
Registers
General purpose 31 (G0 = 0; non-global registers use register windows)
Floating point 32 (usable as 32 single-precision, 32 double-precision, or 16 quad-precision)
A Sun UltraSPARC II microprocessor (1997)

The Scalable Processor Architecture (SPARC) is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems. Since the establishment of SPARC International, Inc. in 1989, the SPARC architecture has been developed by its members. SPARC International is also responsible for licensing and promoting the SPARC architecture, managing SPARC trademarks (including SPARC, which it owns), and providing conformance testing. SPARC International was intended to open the SPARC architecture to create a larger ecosystem; and SPARC has been licensed to several manufacturers, including Atmel, Cypress Semiconductor, Fujitsu, and Texas Instruments. As a result of SPARC International, SPARC is fully open, non-proprietary and royalty-free.

The first implementation of the original 32-bit SPARC architecture (SPARC V7) were initially designed and used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. Later, SPARC processors were used in SMP and CC-NUMA servers produced by Sun, Solbourne and Fujitsu, among others, and designed for 64-bit operation.

As of July 2016, the latest commercial high-end SPARC processors are Fujitsu's SPARC64 X+ (introduced in 2014 for its SPARC M10 server)[1] and SPARC64 XIfx (introduced in 2015 for its PRIMEHPC FX100 supercomputer); and Oracle's SPARC M7 (introduced in October 2015 for its high-end servers).

Features

The SPARC architecture was heavily influenced by the earlier RISC designs including the RISC I and II from the University of California, Berkeley and the IBM 801. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

The SPARC processor usually contains as many as 160 general purpose registers. According to the "Oracle SPARC Architecture 2015" specification an "implementation may contain from 72 to 640 general-purpose 64-bit" registers.[2] At any point, only 32 of them are immediately visible to software – 8 are a set of global registers (one of which, g0, is hard-wired to zero, so only seven of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls.

The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from three to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only three to reduce cost and complexity of the design, or to implement some number between them. Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000.

The architecture has gone through several revisions. It gained hardware multiply and divide functionality in Version 8.[3][4] 64-bit (addressing and data) were added to the version 9 SPARC specification published in 1994.[5]

In SPARC Version 8, the floating point register file has 16 double precision registers. Each of them can be used as two single precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers. SPARC Version 9 added 16 more double precision registers (which can also be accessed as 8 quad precision registers), but these additional registers can not be accessed as single precision registers. No SPARC CPU implements quad-precision operations in hardware as of 2004.[6]

Tagged add and subtract instructions perform adds and subtracts on values checking that the bottom two bits of both operands are 0 and reporting overflow if they are not. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

The endianness of the 32-bit SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load/store) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.

History

There have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended precision" floating-point arithmetic to 128-bit "quad-precision" arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.

SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita, Philips, Ross Technology, Sun Microsystems, and Texas Instruments. Newer specifications always remain compliant with the full SPARC V9 Level 1 specification.

In 2002, the SPARC Joint Programming Specification 1 (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements".

At the end of 2003, JPS2 was released to support multicore CPUs. The first CPUs conforming to JPS2 were the UltraSPARC IV by Sun and the SPARC64 VI by Fujitsu.

In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions developed through the processor generations of UltraSPARC III, IV, IV+ as well as CMT extensions starting with the UltraSPARC T1 implementation:

In 2007, Sun released an updated specification, UltraSPARC Architecture 2007, to which the UltraSPARC T2 implementation complied.

In August 2012, Oracle Corporation made available a new specification, Oracle SPARC Architecture 2011, which besides the overall update of the reference, adds the VIS 3 instruction set extensions and hyperprivileged mode to the 2007 specification.[7]

In October 2015, Oracle released SPARC M7, the first processor based on the new Oracle SPARC Architecture 2015 specification.[2]-[8] This revision includes VIS 4 instruction set extensions.

SPARC architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 through the Sun UltraSPARC Architecture implementations.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

SPARC architecture licensees

The following organizations have licensed the SPARC architecture:

Implementations

Name (codename) Model Frequency (MHz) Arch. version Year Total threads[note 1] Process (nm) Transistors (millions) Die size (mm2) IO pins Power (W) Voltage (V) L1 Dcache (KB) L1 Icache (KB) L2 cache (KB) L3 cache (KB)
SPARC (various), including MB86900[note 2] 14.28–40V71987–19921×1=1800–1300~0.1–1.8--160–256----0–128 (unified)nonenone
microSPARC I (Tsunami) TI TMS390S10 40–50V819921×1=18000.8225?2882.5524nonenone
SuperSPARC I (Viking) TI TMX390Z50 / Sun STP1020 33–60V819921×1=18003.1--29314.3516200–2048none
SPARClite Fujitsu MB8683x 66–108V8E19921×1=1------144, 176--2.5/3.3–5.0 V, 2.5–3.3 V1, 2, 8, 161, 2, 8, 16nonenone
hyperSPARC (Colorado 1) Ross RT620A 40–90V819931×1=15001.5------5?08128–256none
microSPARC II (Swift) Fujitsu MB86904 / Sun STP1012 60–125V819941×1=15002.323332153.3816nonenone
hyperSPARC (Colorado 2) Ross RT620B 90–125V819941×1=14001.5------3.308128–256none
SuperSPARC II (Voyager) Sun STP1021 75–90V819941×1=18003.1299--16--16201024–2048none
hyperSPARC (Colorado 3) Ross RT620C 125–166V819951×1=13501.5------3.308512–1024none
TurboSPARC Fujitsu MB86907 160–180V819961×1=13503.013241673.51616512none
UltraSPARC (Spitfire) Sun STP1030 143–167V919951×1=14703.831552130[note 3]3.31616512–1024none
UltraSPARC (Hornet) Sun STP1030 200V919981×1=14205.2265521--3.31616512–1024none
hyperSPARC (Colorado 4) Ross RT620D 180–200V819961×1=13501.7------3.31616512none
SPARC64 Fujitsu (HAL) 101–118V919951×1=1400--Multichip286503.8128128----
SPARC64 II Fujitsu (HAL) 141–161V919961×1=1350--Multichip286643.3128128----
SPARC64 III Fujitsu (HAL) MBCS70301 250–330V919981×1=124017.6240----2.564648192--
UltraSPARC IIs (Blackbird) Sun STP1031 250–400V919971×1=13505.414952125[note 4]2.516161024 or 4096none
UltraSPARC IIs (Sapphire-Black) Sun STP1032 / STP1034 360–480V919991×1=12505.412652121[note 5]1.916161024–8192none
UltraSPARC IIi (Sabre) Sun SME1040 270–360V919971×1=13505.4156587211.91616256–2048none
UltraSPARC IIi (Sapphire-Red) Sun SME1430 333–480V919981×1=12505.4--58721[note 6]1.916162048none
UltraSPARC IIe (Hummingbird) Sun SME1701 400–500V919991×1=1180 Al----37013[note 7]1.5–1.71616256none
UltraSPARC IIi (IIe+) (Phantom) Sun SME1532 550–650V920001×1=1180 Cu----37017.61.71616512none
SPARC64 GP Fujitsu SFCB81147 400–563V920001×1=118030.2217----1.81281288192--
SPARC64 GP -- 600–810V9--1×1=115030.2------1.51281288192--
SPARC64 IV Fujitsu MBCS80523 450–810V920001×1=1130----------1281282048--
UltraSPARC III (Cheetah) Sun SME1050 600JPS120011×1=1180 Al293301368531.664328192none
UltraSPARC III (Cheetah) Sun SME1052 750–900JPS120011×1=1130 Al29--1368--1.664328192none
UltraSPARC III Cu (Cheetah+) Sun SME1056 1002–1200JPS120011×1=1130 Cu29232136880[note 8]1.664328192none
UltraSPARC IIIi (Jalapeño) Sun SME1603 1064–1593JPS120031×1=113087.5206959521.364321024none
SPARC64 V (Zeus) Fujitsu 1100–1350JPS120031×1=1130190289269401.21281282048--
SPARC64 V+ (Olympus-B) Fujitsu 1650–2160JPS120041×1=1904002972796511281284096--
UltraSPARC IV (Jaguar) Sun SME1167 1050–1350JPS220041×2=21306635613681081.35643216384none
UltraSPARC IV+ (Panther) Sun SME1167A 1500–2100JPS220051×2=2902953361368901.16464204832768
UltraSPARC T1 (Niagara) Sun SME1905 1000–1400UA200520054×8=32903003401933721.38163072none
SPARC64 VI (Olympus-C) Fujitsu 2150–2400JPS220072×2=490540422--120–1501.1128×2128×24096–6144none
UltraSPARC T2 (Niagara 2) Sun SME1908A 1000–1600UA200720078×8=64655033421831951.1–1.58164096none
UltraSPARC T2 Plus (Victoria Falls) Sun SME1910A 1200–1600UA2007 2008 8×8=64655033421831 - - 8164096none
SPARC64 VII (Jupiter)[9] Fujitsu 2400–2880JPS220082×4=865600445--150--64×464×46144none
UltraSPARC "RK" (Rock)[10] Sun SME1832 2300????canceled[11]2×16=3265?3962326??32322048?
SPARC64 VIIIfx (Venus)[12][13] Fujitsu 2000JPS2 / HPC-ACE20091×8=845760513127158?32×832×86144none
SPARC T3 (Rainbow Falls) Oracle/Sun 1650UA2007 2010 8×16=12840[14]???? 371?139?8166144none
Galaxy FT-1500 NUDT (China) 1800UA2007? 201? 8×16=12840????????65?16×1616×16512×164096
SPARC64 VII+ (Jupiter-E or M3)[15][16] Fujitsu 2667–3000JPS2 2010 2×4=865---160-64×464×412288none
LEON4 Aeroflex Gaisler 125–1500V8E 2010 1×1=132---???-????????????
R1000 MCST (Russia) 1000JPS2 2011 1×4=490180128-151, 1.8, 2.532162048none
SPARC T4 (Yosemite Falls)[17] Oracle 2850–3000OSA2011 2011 8×8=6440855403?240?16×816×8128×84096
SPARC64 IXfx[18][19][20] Fujitsu 1850JPS2 / HPC-ACE20121x16=164018704841442110?32×1632×1612288none
SPARC64 X (Athena)[21] Fujitsu 2800OSA2011 / HPC-ACE20122×16=32282950587.51500270?64×1664×1624576none
SPARC T5 Oracle 3600OSA2011 2013 8×16=128281500478???16×1616×16128×168192
SPARC M5 Oracle 3600OSA2011 2013 8×6=48283900????16×616×6128×649152
SPARC M6 Oracle 3600OSA2011 2013 8×12=9628?????16×1216×12128×1249152
SPARC64 X+ (Athena+)[22] Fujitsu 3200–3700OSA2011 / HPC-ACE20142×16=322829906001500392?64×1664×1624Mnone
SPARC64 XIfx[23] Fujitsu 2200JPS2 / HPC-ACE22015?1×(32+2)=34203750?1001??64×3464×3412M×2none
SPARC M7[24][25] Oracle 4133OSA201520158×32=25620>10,000????16×3216×32256×2465536
SPARC S7[26][27] Oracle 4270OSA201520168×8=6420????????16×816×8256×2+256×416384
Name (codename) Model Frequency (MHz) Arch. version Year Total threads[note 1] Process (nm) Transistors (millions) Die size (mm2) IO pins Power (W) Voltage (V) L1 Dcache (KB) L1 Icache (KB) L2 cache (KB) L3 cache (KB)

Notes:

  1. 1 2 Threads per core × number of cores
  2. ↑ Various SPARC V7 implementations were produced by Fujitsu, LSI Logic, Weitek, Texas Instruments and Cypress. A SPARC V7 processor generally consisted of several discrete chips, usually comprising an integer unit (IU), a floating-point unit (FPU), a memory management unit (MMU) and cache memory.
  3. ↑ @167 MHz
  4. ↑ @250 MHz
  5. ↑ @400 MHz
  6. ↑ @440 MHz
  7. ↑ max. @500 MHz
  8. ↑ @900 MHz

Operating system support

SPARC machines have generally used Sun's SunOS, Solaris, OpenSolaris or derived as Illumos, but other operating systems such as NeXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux have also been used.

In 1993, Intergraph announced a port of Windows NT to the SPARC architecture,[28] but it was later cancelled.

In October 2015, Oracle announced a "Linux for SPARC reference platform".[29]

Open source implementations

Several fully open source implementations of the SPARC architecture exist:

A fully open source simulator for the SPARC architecture also exists:

Supercomputers

For HPC loads Fujitsu builds specialized SPARC64 fx processors with a new instruction extensions set called HPC-ACE (High Performance Computing – Arithmetic Computational Extensions).

Fujitsu's K computer ranked #1 in TOP500 – June 2011 and November 2011 lists. It combines 88,128 SPARC64 VIIIfx CPUs, each with eight cores, for a total of 705,024 cores – almost twice as many as any other system in the TOP500 at that time. The K Computer was more powerful than the next five systems on the list combined, and had the highest performance-to-power ratio of any other supercomputer system.[30] It also ranked #6 in Green500 – June 2011 list, with a score of 824.56 MFLOPS/W.[31] In the November 2012 release of TOP500, the K computer ranked #3, using by far the most power of the top three.[32] It ranked #85 on the corresponding Green500 release.[33] Newer HPC processors, IXfx and XIfx, were included in recent PRIMEHPC FX10 and FX100 supercomputers.

Tianhe-2 (TOP500 #1 as of November 2014[34]) has a number of nodes with Galaxy FT-1500 OpenSPARC-based processors developed in China. However, those processors did not contribute to the LINPACK score.[35][36]

See also

References

  1. ↑ "SPARC64 X+: Fujitsu's Next Generation Processor for UNIX servers" (PDF). Fujitsu. September 2, 2013. Retrieved May 26, 2015.
  2. 1 2 "Oracle SPARC Architecture 2015: One Architecture ... Multiple Innovative Implementations" (PDF). Draft D1.0.0. January 12, 2016. Retrieved June 13, 2016. IMPL. DEP. #2-V8: An Oracle SPARC Architecture implementation may contain from 72 to 640 general-purpose 64-bit R registers. This corresponds to a grouping of the registers into MAXPGL + 1 sets of global R registers plus a circular stack of N_REG_WINDOWS sets of 16 registers each, known as register windows. The number of register windows present (N_REG_WINDOWS) is implementation dependent, within the range of 3 to 32 (inclusive).
  3. ↑ "SPARC Options", Using the GNU Compiler Collection (GCC), GNU, retrieved January 8, 2013
  4. ↑ SPARC Optimizations With GCC, OSNews, February 23, 2004, retrieved January 8, 2013
  5. ↑ Weaver, D. L.; Germond, T., eds. (1994), "The SPARC Architecture Manual, Version 9" (PDF), SPARC International, Inc., Prentice Hall, ISBN 0-13-825001-4, retrieved December 6, 2011
  6. ↑ "SPARC Behavior and Implementation". Numerical Computation Guide – Sun Studio 10. Sun Microsystems, Inc. 2004. Retrieved September 24, 2011. There are four situations, however, when the hardware will not successfully complete a floating-point instruction: ... The instruction is not implemented by the hardware (such as ... quad-precision instructions on any SPARC FPU).
  7. ↑ "Oracle SPARC Architecture 2011" (PDF), Oracle Corporation, May 21, 2014, retrieved November 25, 2015
  8. ↑ John Soat. "SPARC M7 Innovation". Oracle web site. Oracle Corporation. Retrieved October 13, 2015.
  9. ↑ FX1 Key Features & Specifications (PDF), Fujitsu, February 19, 2008, retrieved December 6, 2011
  10. ↑ Tremblay, Marc; Chaudhry, Shailender (February 19, 2008), "A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC(R) Processor" (PDF), OpenSPARC, Sun Microsystems, retrieved December 6, 2011
  11. ↑ Vance, Ashlee (June 15, 2009), "Sun Is Said to Cancel Big Chip Project", The New York Times, retrieved May 23, 2010
  12. ↑ "Fujitsu shows off SPARC64 VII", heise online, August 28, 2008, retrieved December 6, 2011
  13. ↑ Barak, Sylvie (May 14, 2009), "Fujitsu unveils world's fastest CPU", The Inquirer, retrieved December 6, 2011
  14. ↑ "Sparc T3 processor" (PDF), Oracle Corporation, retrieved December 6, 2011
  15. ↑ Morgan, Timothy Prickett (December 3, 2010), "Ellison: Sparc T4 due next year", The Register, retrieved December 6, 2011
  16. ↑ "SPARC Enterprise M-series Servers Architecture" (PDF), Fujitsu, April 2011
  17. ↑ Morgan, Timothy Prickett (August 22, 2011), "Oracle's Sparc T4 chip", The Register, retrieved December 6, 2011
  18. ↑ Morgan, Timothy Prickett (November 21, 2011), "Fujitsu parades 16-core Sparc64 super stunner", The Register, retrieved December 8, 2011
  19. ↑ "Fujitsu Launches PRIMEHPC FX10 Supercomputer", Fujitsu, November 7, 2011, retrieved February 3, 2012
  20. ↑ http://www.fujitsu.com/downloads/TC/sc11/sparc64-ixfx-sc11.pdf
  21. ↑ https://www.fujitsu.com/global/Images/HC25.27.910-SPARC64.pdf
  22. ↑ https://www.fujitsu.com/global/Images/HotChips24_Fujitsu_presentation.pdf
  23. ↑ http://www.fujitsu.com/global/Images/20140811hotchips26.pdf
  24. ↑ http://swisdev.oracle.com/_files/M7_Preso.pdf M7: Next Generation SPARC. Hotchips 26 – August 12, 2014. Stephen Phillips
  25. ↑ http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-t7-m7-server-architecture-2702877.pdf Oracle's SPARC T7 and SPARC M7 Server Architecture. October 2015
  26. ↑ http://www.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.24-Monday-Epub/HC27.24.30-HP-Cloud-Comm-Epub/HC27.24.330-sonoma.Vinalk-oracle-v3.pdf Hot Chips – August 23–25, 2015 – Conf. Day1 – Oracle’s Sonoma Processor: Advanced low-cost SPARC processor for enterprise workloads by Basant Vinaik and Rahoul Puri
  27. ↑ http://www.theregister.co.uk/2015/08/24/oracle_sonoma_processor_sparc/?page=1 Blueprints revealed: Oracle crams Sparc M7 and InfiniBand into cheaper 'Sonoma' chips
  28. ↑ McLaughlin, John (July 7, 1993), "Intergraph to Port Windows NT to SPARC", The Florida SunFlash, 55 (11), retrieved December 6, 2011
  29. ↑ Project: Linux for SPARC - oss.oracle.com, October 12, 2015, retrieved December 4, 2015
  30. ↑ "TOP500 List (1-100)", TOP500, June 2011, retrieved December 6, 2011
  31. ↑ "The Green500 List", Green500, June 2011
  32. ↑ "Top500 List – November 2012 | TOP500 Supercomputer Sites", TOP500, November 2012, retrieved January 8, 2013
  33. ↑ "The Green500 List – November 2012 | The Green500", Green500, November 2012, retrieved January 8, 2013
  34. ↑ "Tianhe-2 (MilkyWay-2)", TOP500, May 2015, retrieved May 27, 2015
  35. ↑ Keane, Andy, "Tesla Supercomputing" (mp4), Nvidia, retrieved December 6, 2011
  36. ↑ U.S. says China building 'entirely indigenous' supercomputer, by Patrick Thibodeau Computerworld, November 4, 2010
Wikimedia Commons has media related to SPARC microprocessors.
This article is issued from Wikipedia - version of the 11/12/2016. The text is available under the Creative Commons Attribution/Share Alike but additional terms may apply for the media files.