Load/store architecture

In computer engineering, a load/store architecture divides instructions into 2 categories: memory access (load and store between memory and registers), and ALU operations (which only occur between registers).[1]

RISC systems such as PowerPC, SPARC, RISC-V, ARM or MIPS use the load/store architecture.[1]

For instance, in a load/store approach both operands for an ADD operation must be in registers. This differs from a register memory architecture (used by CISC designs such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register.[1]

The earliest example of a load/store architecture was the CDC 6600.[2] Almost all vector processors (including many GPUs[3]) use the load/store approach.[4]

See also

References

  1. 1 2 3 Computer architecture: pipelined and parallel processor design by Michael J. Flynn 1995 ISBN 0867202041 pages 9-12
  2. ↑ Computer architecture: pipelined and parallel processor design by Michael J. Flynn 1995 ISBN 0867202041 pages 54-56
  3. ↑ "AMD GCN reference" (PDF).
  4. ↑ Memory systems and pipelined processors by Harvey G. Cragon 1996 ISBN 0867204745 pages 512-513


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